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The ADVA004 CDS based Readout Pipeline has the lowest temporal noise in the industry, the noise level is 40uV. The design is very compact and low power.
The Readout (RO) Pipeline can be connected to any 4T pixel array. Advasense delivers a soft IP Block or hard IP block that can be replicated to cover the entire pixel array. Advasense can port the design to a specified CIS process.
The RO pipeline can enable companies the best performing 4T pixel based CIS products.
Advasense also offers its innovative FCP IP - the ADVA001 - that paves the way to a pixel smaller than 1.1u with high FWC that can not be achieved with 4T pixel design.
The ADVA004 is based on the ADVA003 CDS Readout IP and the ADVA002 12Bits 2nd order sigma delta IP (which are also available separately).
ADVA004 IP - Key Specifications:
Readout noise level is 40uV
Column level ADC- 2nd order sigma delta, 12bits (resolution versus
speed is scalable via decimation filter length),
Conversion time is less than 2usec.
CDS operation
Easily connected to any 4T pixel array
Low power and compact design
Low level timing and control included
Test bench and system model are provided for chip level verification
Readout can be 2 sides or one side
Soft IP Block or Hard IP block
For further information please contact us at: info@advasense.com
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